On the Design of Fast , Easily Testable ALU

On the design of fast, easily testable ALU's

A design methodology for implementing fast, easily testable arithmetic-logic units (ALU’s) is presented. Here, we describe a set of fast adder designs, which are testable with a test set that has either ( ) complexity (Lin-testable) or (1) complexity (C-testable), where is the input operand size of the ALU. The various levels of testability are achieved by exploiting some inherent properties of...

Design of a fast, easily testable ALU

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity pres...

Designing of Testable Reversible QCA Circuits Using a New Reversible MUX 2×1

Recently testing of Quantum-dot Cellular Automata (QCA) Circuits has attracted a lot of attention. In this paper, QCA is investigated for testable implementations of reversible logic. To amplify testability in Reversible QCA circuits, a test method regarding to Built In Self Test technique is developed for detecting all simulated defects. A new Reversible QCA MUX 2×1 desig...

Designing of Testable Reversible QCA Circuits Using a New Reversible MUX 2×1

Recently testing of Quantum-dot Cellular Automata (QCA) Circuits has attracted a lot of attention. In this paper, QCA is investigated for testable implementations of reversible logic. To amplify testability in Reversible QCA circuits, a test method regarding to Built In Self Test technique is developed for detecting all simulated defects. A new Reversible QCA MUX 2×1 desig...